1. Field of the Invention
This invention generally relates to refresh memory capacitor, and more particularly to independently refresh memory capacitors without an address driver and latch.
2. Description of Related Art
Memory devices storing data are indispensable to personal computers and other electronic equipment. Memory devices include two main categories: Read Only Memory (ROM) and Random Access Memory (RAM). RAM is readable and rewritable. Dynamic RAM (DRAM) can represents binary data (0 or 1) by using capacitors storing or not storing charges. A capacitor represents a bit, where a capacitor with charges represents a binary “1”; a capacitor without charges represents a binary “0”. A byte usually being used as a unit for digital date storage consists of eight bits. A unit for digital data storage in a memory device is called a memory cell. Memory cells are arranged in arrays. The combination of a specific column and a specific row represent an address for a specific memory cell. Memory cells in the same column or same row are serial-connected by a common conducting line.
The word “Random” in Random Access Memory means that this type of memory cell in DRAM allows to be read from any memory address; “Access” means DRAM is readable and rewritable, which is the major difference from ROM. A memory device consists of a plurality of memory cells. A conventional method for accessing a specific memory cell is the row-column addressing method, which orderly decodes the row address and the column address of the specific memory cell.
Referring to FIG. 1, which is a structural view depicting a 2 KB memory. First, a row address signal 118 is sent. At the same time a row enable signal 115 is sent to activate the row address decoding latch (a row decoder driving signal) in order to enable the 6×64 row decoder 106. The 6×64 row decoder 106 decodes the row address signal to obtain the row address and sends the row address to the memory. Row 27 is exemplary as depicted in FIG. 1. After decoding the row address, a column enable signal is sent to activate the column address decoding latch (a column decoder driving signal) in order to enable the 6×64 column decoder 103. The 6×64 column decoder 103 decodes the column address signal to obtain the column address and sends the column address to the memory. Notice that column 35 is exemplary in FIG. 1. After obtaining the column and column addresses, the memory cell 109 at address 27×35 is found, and is ready to be accessed later.
The Row Address Strobe (RAS) comprises the first step for memory address decoding; whereas the Column Address Strobe (CAS) comprises the second step for memory address decoding and memory accessing. The step of RAS further comprises decoding and latching, which requires an address latch and an address driver. The address latch is a circuit to maintain the present status via triggering clock or recovered control signal before receiving the next clock signal even input changes. Hence, the row address is latched until the column address is acquired.
FIG. 2 is a block diagram of a conventional apparatus for refreshing memory capacitors. Referring to FIG. 2, while refreshing the memory capacitors, refresh controller 204 will output a refresh control signal to trigger the refresh counter 202 outputting a refresh address signal to the address driver 206. Then the address driver 206 outputs an address driving signal to the row address pre-decoder 210. The row address pre-decoder 210 outputs a pre-decoded row address to the pre-decoded row address re-driver 214 for re-driving. Then the re-driven pre-decoded row address is sent to the core device 212 to refresh the memory capacitor. While reading/rewriting the memory cell, the address register 208 provides the address driver 206 with an address signal. Then the reading/rewriting operation can be performed via the row address pre-decoder 210, the pre-decoded row address re-driver 214, and the core device 212.
It is required to use an address driver in the conventional method while refreshing the capacitors or accessing the memory cells. However, the address driver is a power-consuming device, thus it is worth considering to reduce power consumption during standby mode from this point of view.